Hardwired Control Unit

  1. When the control signals are generated by hardware using conventional logic design techniques,the control unit is said to be hardwired.
  2. It is implemented as logic circuits (gates, flip-flops,decoders etc.) in the hardware.
  3. It can be viewed as a state machine that changes from one state to another in every clock cycle


  • Hardwired Control Unit is fast because control signals are generated by combinational circuits.
  • The delay in generation of control signals depends upon the number of gates.
  • Minimizes the average number of clock cycles needed per instruction.
  • occupies a relatively small area (typically 10%) of the CPU chip area.


  • More is the control signals required by CPU; more complex will be the design of control unit.
  • Modifications in control signal are very difficult. That means it requires rearranging of wires in the hardware circuit.
  • It is difficult to correct mistake in original design or adding new feature in existing design of control unit.

Organization of Hardwired control unit

Control unit consist of a:

  • Instruction Register
  • Number of Control Logic Gates,
  • Two Decoders
  • 4-bit Sequence Counter
  1. An instruction read from memory is placed in the instruction register (IR).
    The instruction register is divided into three parts: the I bit, operation code, and address part.
  2. First 12-bits (0-11) to specify an address and are applied to the control logic gates.
  3. Next 3-bits(12-15) to specify the operation code (opcode) field of the instruction and are decoded by 3*8 Decoder. Last left most bit specify the addressing mode I.
    I = 0 for direct address
    I = 1 for indirect address
  4. The 4-bit sequence counter SC can count in binary from 0 through 15.
  5. The counter output is decoded into 16 timing pulses T0 through T15.
  6. The sequence counter can be incremented by INR input or clear by CLR input synchronously.

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